Many different applications in which various processes use the same memory to exchange data with one another are known from the related art. One example of such processes is a central processing unit (CPU) and any peripheral device, both of which access the same random access memory (RAM) to exchange data between the CPU and the peripheral device.
If the data to be exchanged when accessing the same message memory from a plurality of processes are in the form not only of individual memory words but also of data packets, each having a plurality of words, the question of data consistency and data integrity becomes more important. Data consistency is violated when, for example, one process is reading a certain data packet while another process is altering the same data packet. The reading process in such a case may receive a data packet composed of a mixture of old and new memory words. This may result in serious problems in further processing of the contents of the data packets.
To prevent this, methods are known from the related art by which one of the two processes observes the other process prior to accessing a data packet and, if necessary, waits until the other process has concluded its access. As an alternative, one process may also block access by the other process, but this may result in data loss if the blocked process is unable to save its data before its buffer memory has to be used for other tasks. In addition, there are also other methods, by which at least one of the two processes accesses the memory only indirectly, a separate memory management control system storing the data packets in a consistent form in the memory and then retrieving the data packets from the same memory. However, this is relatively complicated and expensive. These known methods may be combined with multiple storage of data packets.
In addition, a communication module in the form of a so-called FlexRay communication controller (CC) is from the related art. The communication module is used to connect the FlexRay communication medium over which messages are transmitted, i.e., the data bus, to a FlexRay node. A corresponding communication controller for use in FlexRay in particular is discussed in DE 10 2005 034 744 A1, for example. For transmitting messages between the node and the communication medium, a specially designed configuration is provided in the communication controller for storing messages. The transmission of messages and management of the memory are controlled by a state machine.
Two so-called transient buffers (TBF), one for channel A and the other for channel B, are provided in the communication controller known from the related art. Each transient buffer may store two messages, namely an Rx (receive) message and a Tx (transmit) message. The interface module also includes a so-called input buffer (IBF) and an output buffer (OBF), each having a capacity of two messages.
The transient buffer (TBF) is accessed first from the communication medium and second via a so-called message handler of the FlexRay communication controller. The input and output buffers (IBF; OBF) are accessed first by the host CPU of the node and second by the message handler. When accessing the above-mentioned buffer of the communication controller from the aforementioned processes, it is a very important prerequisite to maintain data consistency and integrity. For this reason, with the known communication controller, the host CPU does not have any direct access to the message memory (IBF; OBF). The input and output buffers instead have two separate memory blocks (so-called IBF and IBF shadow and OBF and OBF shadow). To send data, the host CPU writes data into the input buffer and then initiates a message transfer. Next the content of the IBF and the IBF shadow are exchanged. Then the transmission of data from the IBF shadow into the message memory (so-called message RAM) begins. The host CPU may write the data from the following message directly into the input buffer (IBF), while the data transmission from the IBF shadow to the message RAM is still underway. The data from the message RAM is then transmitted via the communication medium to other nodes. After the end of the data transmission between the IBF shadow and the message RAM, the contents of IBF and the IBF shadow are exchanged again, and so forth.
Due to this relative complex measure, data integrity may be ensured, but this measure demands a large amount of chip area because each message memory (IBF, OBF) must be present in duplicate. Additional disadvantages of the known communication controller include the fact that the message handler is a relatively large so-called state machine which is therefore expensive. Furthermore, the method described here results in both present data and older data being stored in the message memory (message RAM). In addition, access by the host CPU to the message RAM via the input and output buffers (IBF, OBF) is relatively complex because direct access is impossible and instead only indirect access via IBF shadow and OBF shadow are possible.